Designed and synthesized an Improved Custom Nano Processor on a Xilinx Basys 3 FPGA. This project upgraded a foundational architecture by integrating a fully functional Arithmetic and Logic Unit (ALU) and an extended instruction set for more complex operations.
System Scope & Features
- Expanded Architecture: Supports immediate loads, arithmetic (
ADD,SUB,NEG), bitwise logic, hardware multiplication (MUL), and conditional branching (JZR). - Hardware Diagnostics: Features real-time debugging by mapping processor flags (Zero, Overflow, Comparators) and register contents directly to onboard LEDs and a 7-segment display via a custom decoder.
- Synchronous Execution: Operates on a stable 10 MHz clock (scaled from an onboard 100 MHz oscillator) to execute instructions sequentially from a dedicated
Program_ROM.
Skills & Takeaways
- FPGA Synthesis: Gained hands-on experience mapping internal HDL signals to physical hardware using Vivado constraints.
- Digital Design: Mastered synchronous state management, sequential logic execution, and clock division.
- Low-Level Debugging: Analyzed hardware instruction loops, troubleshooting flag dependencies, and decoding assembly-level bit layouts.